A computer system includes a set of interconnected components or modules of three basic types: central processing unit (CPU), memory, and input/output (I/O). The modules of the computer system are connected together by communication pathways known as busses. A bus is a shared transmission medium in that plural computer modules can transmit across the same bus. However, if two modules transmit during the same time period, their signals will overlap and become garbled. Therefore, it is important to ensure that only one module transmits across the bus during a given time period.
The central processing unit or processor communicates with the memory and I/O modules of the computer system using information transfers known as transactions. Each transaction includes a transaction request in which one of the computer system modules, such as the computer processor, requests the transfer of information to or from another one of the modules. For example, the computer processor could issue a transaction request that writes data to or reads data from the memory module. Each transaction also includes a transaction response that responds to the transaction request or indicates that an error has occurred.
Many computer processors, such as the Intel Pentium Pro processor, issue transaction requests in a pipelined manner in which plural transaction requests are outstanding simultaneously. For example, the Pentium Pro processor bus allows up to eight transactions to be outstanding simultaneously. With such a pipelined system, care must be taken to ensure that the transaction requests are responded to in the same order as they were issued.
Shown in FIG. 1 is a prior art computer system 10 that includes a processor bus 12. The computer system 10 includes a multiprocessor system architecture in which first and second computer processors 14, 16 are each coupled to the processor bus 12. Coupled to the first computer processor 14 is an input device 18, such as a keyboard, mouse, or microphone, that inputs information to the first computer processor from a user. The computer system 10 also includes first and second bus agents 20, 22 coupled to the first and second computer processors 14, 16 via the processor bus 12. Coupled to the first bus agent 20 is a Peripheral Component Interconnect (PCI) bus 24 which is coupled via a video controller 26 to a video monitor 28 that outputs information to the user. An Industry Standard Architecture (ISA) bus 30 also is coupled to the PCI bus 24 via a PCI/ISA bridge 32. Coupled to the ISA bus 30 are a hard drive 34 and a fax/modem 36. Coupled to the second bus agent 22 is a main memory 38.
Whenever either of the first and second computer processors 14, 16 desires to transmit information to or receive information from one of the computer devices 26, 34-38 the computer processor issues a transaction request as discussed above. In prior art computer systems, such as the computer system 10 shown in FIG. 1, the first and second processors 14, 16 and the first and second bus agents 20, 22 include transaction queues 40, 42, 44, 46, respectively, that each keep track of the outstanding transactions of the computer system 10. For example, if the first processor 14 issues a transaction request to read data from the hard drive 34, the first and second processors 14, 16 and the first and second bus agents 20, 22 insert an indication of the transaction request in their respective transaction queues 40-46. Each of the first and second processors 14, 16 and the first and second bus agents 20, 22 includes logic that prevents the transaction requests from being responded to out of the sequential order in which the transaction requests are inserted in the respective transaction queues 40-46. Thus, the transaction queues 40-46 ensure that the various transaction requests transmitted by the processors 14, 16 and bus agents 20, 22 are answered with transaction responses in the same order as the transaction requests were issued.
Although the transaction queues 40-46 enable each of the first and second processors 14, 16 and the bus agents 20, 22 to process a single transaction concurrently, none of the processors 14, 16 or bus agents 20, 22 can process plural transaction requests concurrently. For example, if the first processor 14 issues a transaction request to read data from the hard drive 34 and the second processor 16 subsequently issues a transaction request to write data to the video controller 26, the two transactions cannot be processed concurrently by the video controller 26 and the hard drive 34. Instead, the first bus agent 20 will wait until after the hard drive 34 has issued a transaction response in response to the first transaction request and the bus agent has forwarded the transaction response of the processor bus 12 to the first processor 14 before transmitting the second transaction request to the video controller 26. The first bus agent 20 will wait to send the second transaction request to the video controller 26 even if the video controller 26 is so much faster than the hard drive 34 that the video controller could respond to the second transaction request before the hard drive 34 could respond to the first transaction request.
If the first bus agent 20 transmitted the second transaction request before receiving the response to the first transaction request, then the first bus agent could transmit the second transaction response on the processor bus before transmitting the first transaction response. Transmitting the transaction responses out of order like that would cause the first processor 14 to incorrectly receive the second transaction response in response to the first transaction request. As such, the first processor 14 would be expecting data read from the hard drive 34 and instead would receive the second transaction response from the video controller indicating that data was correctly written to the video controller. Such transposing of transaction responses could quickly disable the computer system 10.